[Video] Linus was right.

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[Video] Linus was right. 1
[Video] Linus was right. 2
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24 Comments on “[Video] Linus was right.”

  1. I still don't know what was Linus right about. AD, F* Nvidia, AD, ECC RAM, AD, elections, AD, cosmic rays, AD, ECC RAM, AD … lost it completely.

  2. I have a 2nd hand 4gb ddr3 stick that sometimes turn off all the other cpu cores except for 1. I have used that ram on an i5 2nd gen cpu with HDD and a system with i7 3rd gen with SSD (the other component I took from the i5 system is the brand new video card, the rest is different).
    I can't notice it when it happens when I'm just browsing fb or watching youtube but when gaming my fps will suddenly drop from 80 to 15 fps because of extreme cpu bottleneck.

  3. Servers use ECC because one of them crashing might interupt hundreds or thousands of users and cost money, its nearly pointless in a desktop PC where if you had to spend the extra money you would just buy sticks stable at higher clocks, Pointless rant is pointless

  4. This Linus failed to mention that, as a reason to use it for consumer machines, more importantly, memory errors can change the values of data that you're working on. So, it can introduce errors into your documents/code/images/models/etc. And, BITD, all IBM PCs / PS/2's and compatibles had parity bit memory (ECC wasn't supported, so no correction). It was actually a differentiator between IBM PC memory and 68000-based PC (Amiga / Atari ST/STe/Mega/TT/Falcon / Macintosh) memory.

    A large scale test was performed in 2009, which found that 8% of DIMMs were affected by errors *every year*.

  5. As you say, ECC using 9 bits (simple parity) uses "tricks" to correct bit errors. The problem with traditional (old skool) single bit parity is, if you have two bits fail the same way, the parity has a chance of being correct.

    An early single bit failure caused a massive banking issue and it was tracked to the phosphor bronze/gold plating on the ceramic ram die cover, it was releasing harmless alpha radiation that was striking the memory cell randomly, flipping bits.

    Years back (vintage late 1970's), EMI Medical used actual ECC (Error Checking and Correction) on its flagship Super Mini SEM-500 Computer. A +6 foot tall by 3 foot wide thing of beauty, nearly on par with the Cray-1 minus the ECL (Emitter Coupled Logic) speed enhancement and fancy I/O. It was so fast that it even suffered from the same propagation delay issues on the wire-wrapped cards. An example of this was when a batch of cards were wire-wrapped using the wrong database and suffered from bizarre and random data errors – only during actual operation – but not during normal diagnostics. This, of course, was frustrating to us "Super Techs" attempting to repair these things – lol.

    What had happened was, two wire-wrap lists were created:
    1.) was the correct version that accounted for wire length in terms of pico-seconds and gate latching speeds (74L$ technology)
    2.) was created for streamlined QA personnel resistance checking to make certain the pins were actually connected to the correct place.

    A board wired under "1" might have a configuration like this:
    I = Input
    O = Output
    # = test point on the edge of the card opposite the edge card connector


    I-O-I-# (sort of a star configuration)

    Where a board wired under "2" might look like this with each input timing getting skewed more and more:

    On a 25"x18" PCB, one of those runs between the inputs might be a diagonal across the board and that was that, flakey operation.
    I was the one to discover this when I had to replace a pin in one of the sockets (Cambion !) and when I unwrapped the 5 wires, I discovered they were obviously not wired correctly.
    (but, I digress)

    It was completely custom and ran using ferrite core or 1K bit Mostek Dynamic Ram IC's in a 16K x 21 bit configuration.
    Since it was hardware ECC, it used the 5 extra bits as an encoded value (Hamming I think) that could correct any 1 bit errors and detect 2 bit errors on the fly, meaning that there was no physical delay between memory valid timing and bus read. This was accomplished via ROM lookup tables that validated – or corrected – the data as it passed through the gates. The data was always "corrected" – there being no "clock" besides the bus read signal and validation status bits* – used to inform the operator that an error had occurred and a tech needed to be called.

    *Status bits:
    1 for a memory fault
    1 for data valid (corrected or correct)

  6. Could this channel stop using clickbaits? I want to know what video I'm about to watch, and don't watch most of your videos when I can't figure out what they are about…………

  7. You can push the timings on ECC way past what you can with normal RAM, so you can actually get the timings lower with ECC. Of course, you'll be pushing them into failure and consuming their ability to correct errors in the process.

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